Integrated circuit Central Processing Unit (CPU) architecture has passed a point of diminishing returns. CPUs require greater and greater die surface area for linear increases in clock speed and not necessarily corresponding increases in processed instructions. Present CPUs provide one to three billion instructions per second (1 to 3 GIPS) best case, yet under typical operating conditions these CPUs achieve at most 10% to 20% of their theoretical maximum performance.
Thus there exists a need for a CPU architecture that requires less die surface area and provides a greater theoretical maximum performance and greater performance under typical operating conditions.